1. Field of the Invention
The present invention illustrates non-volatile memory (NVM), and more particularly, non-volatile memory using a multi-cells selection method to increase the operation window.
2. Description of the Prior Art
Memory is widely used in various electronic devices for data storage in recent years. Like memory cards in digital cameras, random access memory (RAM) and flash memory in computers, memory is manufactured in the form of an integrated circuit for electronic applications. Generally, memory can be classified into two types, named volatile memory (VM) and non-volatile memory (NVM). As it is well known in the art, non-volatile memory has an electronic property that data stored in the non-volatile memory will not volatilize after power is turned off. This electronic property makes non-volatile memory receive more attention in the use of hard disk (HD) drives, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory.
As aforementioned, non-volatile memory is manufactured as an integrated circuit, where the circuit includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. Specifically, the plurality of bit lines are coupled to the plurality of rows of memory cells. The plurality of word lines each coupled to a corresponding row of memory cells. When the word line enables the corresponding row of memory cells, the data can be accessed (erased/written) to the corresponding row of memory cells through the bit line. With enabling the memory cells row by row, data can be sequentially accessed to all the memory cells.
Please refer to FIG. 1. FIG. 1 illustrates the layout structure of a conventional non-volatile memory. In FIG. 1, each word line controls the floating gates of a corresponding row of memory cells. For example, the word line WL1 controls the first row of floating gates FG11 to FG15 with respect to the first row of memory cells. The word line WL2 controls the second row of floating gates FG21 to FG25 with respect to the second row of memory cells. The word line WL3 controls the third row of floating gates FG31 to FG35 with respect to the third row of memory cells. The word line WL4 controls the fourth row of floating gates FG41 to FG45 with respect to the fourth row of memory cells. Since the floating gate controls the input current of the corresponding memory cell, the word lines WL1 to WL4 respectively control the first to the fourth row of memory cells for accessing data by operating on the corresponding floating gates.
Particularly, in conventional non-volatile memory, since the input current for accessing data in each memory cell is small, as time passes by, the voltage offset (i.e., the offset of threshold voltage in each memory cell for data accessing) increases and results in narrowing the operation window of memory, lowering endurance of memory.
Please refer to FIG. 2. FIG. 2 depicts the current distribution of the conventional non-volatile memory in one operation instance. The Y-axis (vertical axis) denotes the number of memory cell and the X-axis (horizontal axis) denotes the un-normalized current intensity of each memory cell. In FIG. 2, the current distribution is presented as a line with circular markers. Specifically, the current distribution has two peak regions P1 and P2. Each peak region locates the local maximum of the distribution curve. The first peak region P1 denotes the number of memory cell used for accessing the low voltage data. The second peak region P2 denotes the number of memory cell used for accessing the high voltage data. The difference of the current of the memory cell between a first value within the first peak region P1 (i.e., within the current intensity interval 1 to 6 in X-axis) and a second value within the second peak region P2 (i.e., within the current intensity interval 26 to 31 in X-axis) is defined as the operation window. In FIG. 2, the first value is chosen to be about 4. The second value is chosen to be about 30. Apparently, Since the word lines enables the conventional non-volatile memory cells row by row, the operation window in FIG. 1 has a narrow width and thus results in low tolerance of the voltage offset through the use of time, leading to low endurance of the non-volatile memory.
To improve the endurance of memory, a prior art method has been developed. The main idea is to use a metal jumper to connect the ends of some of the bit lines together, causing the connection of bit lines to be fixed.